In the continuing effort to increase the storage capacity of hard disk drives, one area of development has focused on decreasing the rise time (or, equivalently, increasing the “slew rate”) of the write current applied to the magnetic head. Generally speaking, if the rise time can be decreased, then it is possible to record more data bits per second on the hard disk drive, resulting in increased storage capacity.
One way in which rise time has been increased is through a preamplifier drive circuit that deliberately boosts the write current above the target value, for a short boost period at the beginning of the write period. During the boost period, the drive circuit provides additional current so as to cause a deliberate (but short) overshoot in the amount of current supplied to the write head. This increased current during the boost period decreases rise time at the write head, and permits increased storage capacity of the disk.
FIG. 1 is a simplified circuit showing this effect, and FIG. 2 is a timing diagram for the FIG. 1 circuitry. In this regard, the invention was developed in connection with a preamplifier for the write head of a hard disk drive, which is an inductive load. It will be appreciated, however, that the invention has application to drive circuits for transmission lines generally, regardless of whether the driven load is or is not the head of a hard disk drive, and regardless of whether the driven load is or is not an inductive load. Accordingly, and unless otherwise noted, this specification will describe the load as a purely resistive load, and the transmission line as any generalized transmission line.
Turning to FIG. 1, a load RL at the end of a transmission line TL is driven by a drive circuit 1. Drive circuit 1 includes a pair of series-connected current sources IW connected between positive supply voltage VDD and negative supply voltage VEE. In the case of driving the head of a hard disk drive, these current sources provide a write current. Switch S2 controls current supplied by the first current source IW, so as to supply a positive-going current to the load RL, and switch S4 controls current supplied by the second current source IW, so as to supply a negative-going current to load RL. Switch S1 is operated for a short boost period TB during a positive-going signal period, and switch S3 is operated for a short boost period TB during a negative-going signal period. A termination resistor RT is provided for impedance-matching to the impedance Z0 of transmission line TL. (B) signifies a connector between drive circuitry 1 and the transmission line TL.
FIG. 2 is a timing diagram that depicts operation of drive circuitry 1 in FIG. 1. Because of pervious operations in the circuitry, the timing diagram of FIG. 2 commences at a state in which switches S1, S2 and S3 are open, and switch S4 is closed. In this state, the voltage at connector (B) has reached a steady state, corresponding to a desired negative-going current IL flowing through load RL.
At this time, a positive-going current is needed for load RL. Accordingly, switch S4 is opened, and both of switches S1 and S2 are closed. Switch S2 causes current from current source IW to flow, and switch S1 causes a boosted current to flow. As a consequence, the voltage at connector (B) rises almost immediately to VDD, which corresponds to a voltage that is VDS higher than the ultimate driving voltage that is needed.
Switch S1 is maintained in the closed state for a boost period TB that is shorter than the delay time TD of transmission line TL. At the expiration of the boost period TB, switch S1 is opened, which allows voltage at connector (B) to fall to the needed voltage.
Meanwhile, the applied voltage travels down the transmission line TL where, after the propagation delay of the transmission line, it appears as a boosted current across the load RL. Likewise, after the boost period TB has expired, current IL through the load RL decreases to the intended target of IW.
As a consequence of this operation, there is a decrease in the rise time of current IL through load RL, as measured from its previous value of −IW to the target value of +IW is decreased, relative to the rise time without the boosted signal. This permits higher density recording on a hard disk drive.
In practical devices, switches S1 through S4 are implemented in MOS or bipolar transistor fabrication, and such transistors cannot withstand the large voltage swings that occur in the transition between positive-going and negative-going current flow. For example, in the instant between the time where S4 opens and S2 closes, switch S2 will see the entire voltage drop of (VEE-VDD) across it. MOS or bipolar transistor devices cannot withstand such a large voltage across them without damage.
Accordingly, in real-world devices, a protection device is provided for these switches. FIG. 3 illustrates the use of such a protection device.
FIG. 3 shows only the upper half of driver circuitry 2, which is largely similar to the upper half of driver circuitry 1 except for the introduction of protection device M1. The protection device M1 is ordinarily a large p-type device, with its gate tied to VSS. The M1 protection device operates as follows. Consider a situation in which the voltage at connector (B) has been operating at VDD, corresponding to a positive-flowing current, and a transition to a negative-flowing current is desired. In this case, the voltage at connector (B) switches from VDD to VEE (approximately). Without protection device M1, switches S1 and S2 would see the entire voltage swing of (VEE-VDD), which might tend to damage the devices. On the other hand, because of the presence of protection device M1 and because its gate is tied to VSS, the voltage at the source of protection device M1 (corresponding to point (A)) cannot go below VSS. Thus, the voltage across protection device M1 is acceptable, and the voltage across switches S1 and S2 is also acceptable.
While the protection device M1 is a desirable addition, its introduction into the drive circuitry causes difficulties. Specifically, the protection device M1 is a large device since there is an intention to provide large currents (such as 60 milliamps) to the load RL. Because the protection device M1 is a large device, its parasitic capacitance C1 is also large. During the boost period TB, switch S1 is on and the voltages at points (A) and (B) are both raised to VDD, which drives the protection device M1 in its linear region. After the boost period TB, switch S1 opens and the voltage at point (B) drops to a value that depends on the impedance Z0 of the transmission line TL and on the current IW provided by the current source. For typical large values, such as a current IW=40 milliamps to 60 milliamps and impedance Z0=approximately 100 ohms, the voltage at point (B) is around 2 volts. Meanwhile, protection device M1 is still in its linear region. Thus, when a reflection from the load RL arrives back from the transmission line at point (B), it sees the termination resistor RT in parallel with resistor RON (which is the on-resistance of device M1), plus the parasitic capacitance C1. This is no longer a match to the impedance Z0 of the transmission line TL, and thus causes a pulse-like disturbance whose size is Γ·VDS, as shown in FIG. 2, where “Γ” is a reflection coefficient. The disturbance is shaped to the same as the boost pulse, and for its part, the disturbance causes an additional re-reflection back to the load RL. This undesirable re-reflection is shown in FIG. 4.